Homework 1 - EE4109-2020-2021
Design of a CS stage
Design of two CS stages:
- A CS stage that can drive the load of the active antenna
- A CS stage that can be used as low-noise input stage
Presentation
The presentation “Structured electronic design EE4109 2020-2021” illustrates the way in which the two CS stages should be designed.
Videos
- EE4109 2020 9_1: Homework 1, Design of a CS stage, Design Tasks
- EE4109 2020 9_2: Homework 1, Design of a CS stage, Load drive requirements
- EE4109 2020 9_3: Homework 1, Design of a CS stage, Output stage drive requirements
- EE4109 2020 9_4: Homework 1, Design of a CS stage, Driving the output stage
- EE4109 2020 9_5: Homework 1, Design of a CS stage, Test benches output stage
- EE4109 2020 9_6: Homework 1, Design of a CS stage, Input stage design
- EE4109 2020 9_7: Homework 1, Design of a CS stage, LTspice noise test bench
- EE4109 2020 9_8: Homework 1, Design of a CS stage, Homework remarks