Lecture 9: 01-12-2020¶

Homework 1 - EE4109-2020-2021

Design of a CS stage

Design of two CS stages:

1. A CS stage that can drive the load of the active antenna
2. A CS stage that can be used as low-noise input stage

Presentation

The presentation “Structured electronic design EE4109 2020-2021” illustrates the way in which the two CS stages should be designed.

Videos

1. EE4109 2020 9_1: Homework 1, Design of a CS stage, Design Tasks
2. EE4109 2020 9_2: Homework 1, Design of a CS stage, Load drive requirements
3. EE4109 2020 9_3: Homework 1, Design of a CS stage, Output stage drive requirements
4. EE4109 2020 9_4: Homework 1, Design of a CS stage, Driving the output stage
5. EE4109 2020 9_5: Homework 1, Design of a CS stage, Test benches output stage
6. EE4109 2020 9_6: Homework 1, Design of a CS stage, Input stage design
7. EE4109 2020 9_7: Homework 1, Design of a CS stage, LTspice noise test bench
8. EE4109 2020 9_8: Homework 1, Design of a CS stage, Homework remarks