Location: www (zoom)
Time: 17:45 - 19:30
In the previous lectures we have discussed the design of the voltage and current-drive capability and the noise performance of a CS stage.
Your first design task is to determine the design parameters \(W,\,L,\,I_{DS},\,V_{DS}\) for two CS stages:
A CS stage (CMOS18) that can drive the load of the active antenna.
Please consider that the cable connected to the output of the active antenna should be driven from its characteristic impedance.
A CS stage of which the equivalent input noise sources are small enough to satisfy the noise requirements of the active antenna.
Over the frequency range of interest the 18cm short rod antenna behaves capacitively. Its capacitance is about 1.5pF.
You can use both SLiCAP and LTspice. The report with your results should be generated with SLiCAP. LTspice output can be included in the html output of SLiCAP as shown in the CS stage exercice. The compressed html directory of SLiCAP should be uploaded in Brightspace.
Your work will be graded with pass/fail. Pass will give you 10% of your total homework grade. For the grading of EE4109 see Brightspace.
